Resume

Current Position

Hybrid
Boxborough, MA
Leading case studies using variety of proprietary models at different levels of abstraction to balance the needs for rapid prototyping as well as accurately predicting bottlenecks and architectural inefficiencies, models written in C++11 and Python3
Creating lightweight and flexible data collection library to enhance ability to quickly collect and collate data simulations using modern C++11 and Rust
Building coprocessor module for proprietary performance modeling simulator in C++11 while extending and refactoring existing modules for greater reuse and reduction of technical debt
Synthesizing and interpreting performance data for case study presentations to designers to forecast next generation of coprocessors using pandas, duckdb, and plotly Python libraries
Two papers accepted to internal conference concerning increasing efficiency and efficacy of methods used in performance modeling

Hybrid
Boston, MA
Reduced time to RTLS (Real-Time Location System) deployments through creation of newly designed GUI tool written in Python and leveraging pandas, numpy, and PyQt libraries
Visualized the health of our RTLS deployments through development of a data-driven dashboard written in Python and leveraging pandas, numpy, dask, and dash libraries
Achieved reuse of common utilities used by R&D team through creation of a Python package, including a submodule implementing an API client for interaction with live RTLS servers
Introduced automation and testing methodologies to reduce technical debt with the creation of a CI flow for three projects, including linting and testing stages

Boston, MA
A company founded in 2017 creating ML accelerator chips using integrated photonics in addition to traditional digital CMOS technology

Remote
Wrote a proprietary microarchitectural simulator in modern C++ using event-driven and OO programming paradigms with a Python front end
Co-designed the final microarchitecture using a novel photonic network-on-chip of a linear algebra accelerator for ML workloads
Conducted interviews resulting in growing the architecture team from 1 to 4 members

On-Site
Promoted efficiency through increased abstraction and automation by writing an extensible Python framework to generate RTL, DV, and C-based driver collateral from industry standard SystemRDL
Bootstrapped gate level simulation (GLS) flow and solely responsible for all GLS verification of Lightelligence’s first test chip

Marlborough, MA
Executed block level verification of the virtual resource manager coprocessor with the focus on the scoreboard in SystemVerilog/UVM
Verified integration and function of distributed support-blocks in all SOC coprocessors at the full chip level by co-writing a simple OS framework and associated test suite in C and SystemVerilog
Reduced debug loop time by catching common syntax errors faster through contribution of new features to internal linting tool written in Python
Mentored college intern through successful delivery of a report aggregation tool eliminating manual effort to collate test reports